The invention relates generally to a method for recovering a pixel clock for generating a digital image from an analog video signal. In particular, the invention relates to a method for adjusting the frequency and the phase of the pixel clock.
Conventional computer monitors are driven by analog video signals, including vertical and horizontal synchronization (sync) pulses. Vertical sync pulses serve as the timing reference for data and other features in each video frame in the analog video signal. Horizontal sync pulses are the timing reference for image data and signal features for each horizontal scanline in the video frame. The position of the image on the monitor can be adjusted automatically or manually by delaying the image data relative to the sync pulses. Minor variations in the shape or center position of the image with respect to the monitor do not significantly affect the appearance of the displayed image.
Recent developments in display device technology have resulted in monitors with fixed spatial resolution, such as flat panel displays and plasma monitors. The analog video signal provided to conventional analog monitors must be converted to a digital format in order to make the fixed resolution display compatible with traditional computer video cards.
Conversion of the analog video signal to digital format requires an accurate pixel clock and knowledge of the geometry of the digital image to be generated. In particular, the pixel clock frequency and the location of the image data in the analog video signal must be accurately known. Manufacturers generally comply with standards and guidelines such as those provided by the Video Electronics Standards Association (VESA). The VESA standard defines various signal characteristics including the front and back porch durations for horizontal scanlines and video frames, the active video portion, and the top, bottom, left and right borders (see VESA and Industry Standards and Guidelines for Computer Display Monitor Timing, Version 1.0, Revision 0.8, September 1998). Unfortunately, knowledge of a particular standard utilized by a display manufacturer is generally not sufficient to determine the required pixel clock necessary to drive the display. For example, front porch and back porch durations for the horizontal scanlines can vary between manufacturers of video cards in general compliance with the same VESA standard. Moreover, even if the pixel clock frequency is correct, an error in the phase of the pixel clock can result in unacceptable image degradation and image position shift.
The present invention relates to a method for converting an analog video signal into a digital format for display on a fixed resolution device. The invention overcomes image degradation associated with analog video signals that vary from standard values for a corresponding video mode.
Conversion of an analog video signal to a digital video signal suitable for a fixed resolution display requires knowledge of the pixel clock parameters used in the video card providing the analog video signal. In addition, knowledge of the active image size and the actual values for the horizontal and vertical front and back porches within a video frame is usually required. In general, the method of the invention includes generation of a pixel clock based on default values specified by an analog video standard. The resulting digital image is evaluated to determine whether the generated pixel clock is satisfactory and, if not, the pixel clock is modified in frequency and/or phase. The resulting modified pixel clock is used to generate another digital image for evaluation. Evaluation includes comparison of the digital image size and the image size specified in the video standard. This process of modifying the pixel clock and evaluating the resulting digital image is repeated until a satisfactory digital image is obtained. Because the method requires performing high-speed calculations during transmission of a video frame and lower speed calculations between video frames, the method can be implemented in both hardware and software. The hardware executes the high-speed processing during a video frame and the firmware conducts the lower speed processing between video frames.
The invention relates to a method for determining a pixel clock frequency. The pixel clock frequency is the rate at which the pixels are sampled from the analog video signal and is equal to the inverse of the sampling time for an individual pixel. An analog video signal is received and the on-transition and off-transition times of an active video portion of the analog video signal are detected. A number of pixels in the active video portion are determined in response to the detected on-transition and off-transition times. The number of pixels in the active video portion is compared with a predetermined pixel number. A modified pixel clock frequency is determined if the number of pixels in the active video portion is not equal to the predetermined pixel number.
In one embodiment, the method includes the additional steps of determining the number of pixels in the active video portion in response to the on-transition and off-transition times and the modified pixel clock frequency, comparing the number of pixels in the active video portion and the predetermined pixel number, and determining a different modified pixel clock frequency if the number of pixels in the active video portion is not substantially equal to the predetermined pixel number. In another embodiment, the step of determining a modified pixel clock frequency includes multiplying the horizontal sync pulse frequency of the analog video signal by a frequency multiplier if the number of pixels in the active video portion is substantially different from the predetermined pixel number.
The invention also relates to a method of adjusting the phase of the pixel clock. The phase of the pixel clock is defined relative to the on-transition time of the active video portion (or other component) of the analog video signal. The phase is changed by advancing or delaying the pixel clock in time relative to the analog video signal. The method includes receiving a first analog video frame signal and converting each of the active video portion of the analog video frame signal to pixel values based on the pixel clock. The method also includes determining a first image coordinate using the pixel values, decrementing the phase of the pixel clock by a first predetermined value, receiving a subsequent analog video frame signal, converting each of the active video portions of the subsequent analog video frame signal to subsequent pixel values based on the pixel clock having the decremented phase and determining a subsequent image coordinate from the subsequent pixel values. The first image coordinate and the subsequent image coordinate are compared and the steps of decrementing the phase of the pixel clock, receiving a subsequent analog video frame signal, converting each of the active video portions of the subsequent analog video frame signal and determining a subsequent image coordinate are repeated if the first image coordinate matches the subsequent image coordinate. If the first image coordinate does not match the subsequent image coordinate, the phase of the pixel clock is adjusted by a second predetermined value. In one embodiment, the second predetermined value is one half the period of the pixel clock.
In another aspect the invention relates to a system for generating a pixel clock. The system includes an analog-to-digital converter, an edge detection module, a processor, a comparator, and a clock generator. The analog-to-digital converter receives an analog video signal at a first input and the pixel clock at a second input, and provides pixel data to the edge detection module. Edge coordinates provided by the edge detection module are provided to the processor and the processor provides the number of pixels in the active video portion of the analog video signal to the comparator. The comparator generates an output signal responsive to the number of active pixels in the active video portion and a reference number of pixels. The processor provides to the clock generator a frequency multiplier signal that is responsive to the output signal from the comparator and edge coordinates. The clock generator generates the pixel clock which is provided as an input signal to the analog-to-digital converter.
In another embodiment the invention relates to a system for adjusting the phase of a pixel clock. The system includes an analog-to-digital converter, an edge detection module, a processor, a memory module and a phase adjuster. The analog-to-digital converter receives an analog video signal and provides pixel data to the edge detection module. Edge coordinates provided by the edge detection module are provided to the processor and the memory module. The memory module provides edge coordinates from prior video frames to the processor. The phase adjuster receives a phase control signal from the processor and the pixel clock, and generates a phase-adjusted pixel clock that is provided at the second input of the analog-to-digital converter.